module MUX_2x1_8bit(i1, i2, out, sel);
  input [7:0]i1, i2;
  input sel;
  output [7:0]out;
  wire [7:0]w1, w2;
  
  and a10(w1[0], i1[0], ~sel);
  and a11(w1[1], i1[1], ~sel);
  and a12(w1[2], i1[2], ~sel);
  and a13(w1[3], i1[3], ~sel);
  and a14(w1[4], i1[4], ~sel);
  and a15(w1[5], i1[5], ~sel);
  and a16(w1[6], i1[6], ~sel);
  and a17(w1[7], i1[7], ~sel);
  
  and a20(w2[0], i2[0], sel);
  and a21(w2[1], i2[1], sel);
  and a22(w2[2], i2[2], sel);
  and a23(w2[3], i2[3], sel);
  and a24(w2[4], i2[4], sel);
  and a25(w2[5], i2[5], sel);
  and a26(w2[6], i2[6], sel);
  and a27(w2[7], i2[7], sel);
  
  or o1(out[0], w1[0], w2[0]);
  or o2(out[1], w1[1], w2[1]);
  or o3(out[2], w1[2], w2[2]);
  or o4(out[3], w1[3], w2[3]);
  or o5(out[4], w1[4], w2[4]);
  or o6(out[5], w1[5], w2[5]);
  or o7(out[6], w1[6], w2[6]);
  or o8(out[7], w1[7], w2[7]);
  
endmodule

module MUX_4x1_8bit(i1, i2, i3, i4, out, sel);
  input [7:0] i1, i2, i3, i4;
  input [1:0]sel;
  output [7:0] out;
  wire [7:0]w1, w2, w3, w4;
  
  MUX_2x1_8bit M1(i1, i2, w1, sel[0]);
  MUX_2x1_8bit M2(i3, i4, w2, sel[0]);
  MUX_2x1_8bit M3(w1, w2, out, sel[1]);  
  
endmodule

module MUX_8x1_8bit(i1, i2, i3, i4, i5, i6, i7, i8, out, sel);
  input [7:0] i1, i2, i3, i4, i5, i6, i7, i8;
  input [2:0]sel;
  output [7:0] out;
  wire [7:0]w1, w2;
  
  MUX_4x1_8bit M1(i1, i2, i3, i4, w1, sel[1:0]);
  MUX_4x1_8bit M2(i5, i6, i7, i8, w2, sel[1:0]);
  MUX_2x1_8bit M3(w1, w2, out, sel[2]);
  
endmodule